1 00:00:00,500 --> 00:00:02,960 Using a D register as the memory component 2 00:00:02,960 --> 00:00:05,695 in our sequential logic system works great! 3 00:00:05,695 --> 00:00:07,070 At each rising edge of the clock, 4 00:00:07,070 --> 00:00:08,880 the register loads the new state, 5 00:00:08,880 --> 00:00:11,280 which then appears at the register’s output 6 00:00:11,280 --> 00:00:15,070 as the current state for the rest of the clock period. 7 00:00:15,070 --> 00:00:18,000 The combinational logic uses the current state and the value 8 00:00:18,000 --> 00:00:21,020 of the inputs to calculate the next state and the values 9 00:00:21,020 --> 00:00:23,450 for the outputs. 10 00:00:23,450 --> 00:00:25,960 A sequence of rising clock edges and inputs 11 00:00:25,960 --> 00:00:28,670 will produce a sequence of states, which 12 00:00:28,670 --> 00:00:31,360 leads to a sequence of outputs. 13 00:00:31,360 --> 00:00:34,160 In the next chapter we’ll introduce a new abstraction, 14 00:00:34,160 --> 00:00:37,260 finite state machines, that will make it easy to design 15 00:00:37,260 --> 00:00:39,490 sequential logic systems. 16 00:00:39,490 --> 00:00:42,370 Let’s use the timing analysis techniques we’ve learned 17 00:00:42,370 --> 00:00:46,070 on the sequential logic system shown here. 18 00:00:46,070 --> 00:00:49,100 The timing specifications for the register and combinational 19 00:00:49,100 --> 00:00:51,150 logic are as shown. 20 00:00:51,150 --> 00:00:54,240 Here are the questions we need to answer. 21 00:00:54,240 --> 00:00:57,020 The contamination delay of the combinational logic isn’t 22 00:00:57,020 --> 00:00:58,590 specified. 23 00:00:58,590 --> 00:01:00,780 What does it have to be in order for the system 24 00:01:00,780 --> 00:01:02,790 to work correctly? 25 00:01:02,790 --> 00:01:05,860 Well, we know that the sum of register and logic 26 00:01:05,860 --> 00:01:08,290 contamination delays has to be greater 27 00:01:08,290 --> 00:01:11,080 than or equal to the hold time of the register. 28 00:01:11,080 --> 00:01:13,750 Using the timing parameters we do know along 29 00:01:13,750 --> 00:01:15,520 with a little arithmetic tells us 30 00:01:15,520 --> 00:01:17,660 that the contamination delay of the logic 31 00:01:17,660 --> 00:01:21,700 has to be at least 1ns. 32 00:01:21,700 --> 00:01:24,360 What is the minimum value for the clock period tCLK? 33 00:01:24,360 --> 00:01:28,280 The second timing inequality from the previous section 34 00:01:28,280 --> 00:01:30,430 tells us that tCLK has be greater 35 00:01:30,430 --> 00:01:33,530 than than the sum of the register and logic propagation 36 00:01:33,530 --> 00:01:37,140 delays plus the setup time of the register. 37 00:01:37,140 --> 00:01:39,310 Using the known values for these parameters 38 00:01:39,310 --> 00:01:41,560 gives us a minimum clock period of 10ns. 39 00:01:41,560 --> 00:01:47,030 What are the timing constraints for the Input signal 40 00:01:47,030 --> 00:01:50,460 relative to the rising edge of the clock? 41 00:01:50,460 --> 00:01:53,450 For this we’ll need a diagram! 42 00:01:53,450 --> 00:01:56,220 The Next State signal is the input to the register 43 00:01:56,220 --> 00:02:00,870 so it has to meet the setup and hold times as shown here. 44 00:02:00,870 --> 00:02:03,330 Next we show the Input signal and how 45 00:02:03,330 --> 00:02:05,240 the timing of its transitions affect 46 00:02:05,240 --> 00:02:07,730 to the timing of the Next State signal. 47 00:02:07,730 --> 00:02:10,680 Now it’s pretty easy to figure out when Input has to be stable 48 00:02:10,680 --> 00:02:15,360 before the rising clock edge, i.e., the setup time for Input. 49 00:02:15,360 --> 00:02:17,410 The setup time for Input is the sum 50 00:02:17,410 --> 00:02:19,510 of propagation delay of the logic 51 00:02:19,510 --> 00:02:22,280 plus the setup time for the register, which 52 00:02:22,280 --> 00:02:25,570 we calculate as 7ns. 53 00:02:25,570 --> 00:02:29,300 In other words, if the Input signal is stable at least 7ns 54 00:02:29,300 --> 00:02:32,820 before the rising clock edge, then Next State will be stable 55 00:02:32,820 --> 00:02:36,780 at least 2ns before the rising clock edge and hence meet 56 00:02:36,780 --> 00:02:40,840 the register’s specified setup time. 57 00:02:40,840 --> 00:02:43,410 Similarly, the hold time of Input 58 00:02:43,410 --> 00:02:45,890 has to be the hold time of the register 59 00:02:45,890 --> 00:02:49,030 minus the contamination delay of the logic, which 60 00:02:49,030 --> 00:02:52,560 we calculate as 1ns. 61 00:02:52,560 --> 00:02:55,230 In other words, if Input is stable at least 1ns 62 00:02:55,230 --> 00:02:58,160 after the rising clock edge, then Next State 63 00:02:58,160 --> 00:03:01,950 will be stable for another 1ns, i.e., a total of 2ns 64 00:03:01,950 --> 00:03:04,210 after the rising clock edge. 65 00:03:04,210 --> 00:03:08,480 This meets the specified hold time of the register. 66 00:03:08,480 --> 00:03:11,900 This completes our introduction to sequential logic. 67 00:03:11,900 --> 00:03:13,810 Pretty much every digital system out 68 00:03:13,810 --> 00:03:16,030 there is a sequential logic system 69 00:03:16,030 --> 00:03:19,060 and hence is obeying the timing constraints imposed 70 00:03:19,060 --> 00:03:21,190 by the dynamic discipline. 71 00:03:21,190 --> 00:03:25,380 So next time you see an ad for a 1.7 GHz processor chip, 72 00:03:25,380 --> 00:03:28,850 you’ll know where the “1.7†came from!